Kedar Gopalakrishna Online Resume

Objective

To obtain a challenging position in the field of VLSI Design where my skills, academic training and experience can be utilized. Areas of interests include logic design, circuit design, validation, synthesis and STA.

Work Experience

Intern (10/11/2010 – 12/21/2011)

Last Employer: LSI Computer Systems

Contact Person: 1-631-271-0400

Responsibilities: * Functional verification of ASIC LS6203 in Verilog XL testing the different modes of operation of the ASIC. * Reduced total testing time by 50%. * ASIC LS6203 is used in fire alarm systems which uses sensors and based on the voltage sensed, produces sirens of different frequencies.

RnD Intern , Processor Group (06/01/2010 – 08/31/2010)

Last Employer: IBM STG

Responsibilities: * RLM and Hybrid design flow for 32nm technology to generate a Layout starting from the VHDL with auto-placement, auto-routing and transistor level timing runs. * Main focus was on synthesis and placement. Pre-placement of the pins and latches, combinatorial logic block placement were done in order to improve timing and area utili-zation. * Parallel work included altering synthesis flow and placement to pick up certain standard cells by generating new synthesis rule and delay rules. * Exposure to simulations on PowerSpice for small combinational blocks. * Attended the Fresh Hire training programs with the regular Employees

Intern , Test Chip Group (02/04/2008 – 07/14/2008)

Last Employer: Infineon Technologies

Responsibilities: * Project focused on both semi-custom and full custom design for the 65nm technology. * Developed an RTL code based on the available specification for Dual Port Memory, run-ning Lint and functional verification using test benches and finding the access times. * RTL, Gate Level Simulations and memory test using March algorithms. * Designed a Full Custom performance block for the qualification of the standard cells on silicon.

RnD Software Engineer (07/15/2008 – 06/30/2009)

Last Employer: Agilent Technologies

Responsibilities: * Involved in testing the User Interface (UI) and the Web Services part of Roaming Man-agement Service software which is used by Telecom providers like AT

Education

Establishment: Stony Brook University

Degree: Master of Science

Education Period: 08/31/2009 - 12/21/2010

Speciality: Electrical Engineering

Average Grade: 3.67 out of 4

Establishment: Sri Jayachamarajendra College of Engineering

Degree: Bachelor of Engineering

Education Period: 09/06/2004 - 06/30/2008

Speciality: Electronics and Communication

Average Grade: 76.8 out of 100

Skills

* Operating System : Microsoft Windows family, Linux * Programming Languages : C, VHDL, Verilog, C++, Data Structures, System C. * Assembly Languages : 8085, 8086, 8051. * Engineering packages : Active-VHDL, Microwind , Cadence: Virtuoso, Sche-matic, Spectre, PowerSpice, Verilog XL, Synopsys Design Compiler, Synopsys Cocentric, Spyglass * Scripting Language : Cadence SKILL

Foreign Language Skills: Fluent in English, Hindi and Kannada both spoken and written.

Additional Information

Research Projects: Design of 16 bit microprocessor: * Development of a five stage pipelined, 16 bit processor executing 40 instructions, using a hierarchical design at transistor‐level in Cadence Virtuoso and Composer Schematic. * Design of schematics, symbols and layouts, for the processor datapath components, register file, ALU, SRAM and pipeline registers. * Synthesis of the datapath/memory controller using Synopsys Design Compiler. * Simulated the circuits using Spectre to get the worst case delays of the cells with parasitic capacitances added. * Simulation of the full datapath in Verisim using Verilog Test benches. Design of pipeline for Cell SPU using Verilog: * Developed a dual-issue pipelined version of the six-seven stage pipelined SPU-Lite pro-cessor with local memory at the register transfer (data flow) level in Verilog. * Special techniques used were dual issue, data forwarding, branch prediction and hint for branch. * Verification performed for the design with a set of test (assembly-level) programs. Design of a 8 bit pipeline Analog to Digital Converter : * Design of a full-fledged 8-bit, 10-MS/s pipelined ADC in a 0.5-μm CMOS technology in Cadence. * A switched-capacitor residue amplifier is used to build the ADC. * Simulation is performed on Spectre to record SNR, SNDR, THD and ENOB. Integrated Circuit Design: * Design of a folded cascode amplifier of a gain >90dB, phase margin <50̊ and power dissipation less than 3mW with design and simulation carried out in Cadence Schematic and Spectre. VLSI design automation: * Partitioning, Placement & Routing Automation to reduce total IC area and reduce the longest interconnect using simulated annealing and Technology Mapping to map gate netlists to a library of gates.

Interests

Active member of IEEE,SJCE, India and have organised technical events in the college .
Actively participated in debates, quiz, mock rock and other literary events at SJCE and have won prizes in the same.
Resident Assistant at Chapin Apartments, SUNY Stony Brook from Jan ‘10 to Jan ‘11.